With the continuous improvement of our living standards and the increasing development of semiconductor technologies, in the future semiconductor market, there will be an increasing demand for the level-up of intelligence and miniaturization of semiconductor packing devices. For example, digital products, such as digital cameras, mobile phones, PDAs and the like will be required to have a smaller size for ease of carrying, diverse functionalities and a high price-performance. In order to meet the demand for the development of intelligence and miniaturization of semiconductor packing devices, there arises a need for multi-chip packaging (MCP) solutions to package two or more planar devices in a stacking-and-connecting way at a wafer level. Such packaging method is also known as three-dimensional (3D) packaging. Currently, there are three major ways to achieve 3D packaging, namely wire bonding, flip chip bonding and through silicon via (TSV) bonding. Among these bonding methods, TSV bonding is considered as one of the most potential and promising 3D packaging methods, because it has many advantages such as a smaller length and a higher density of bonding leads, a smaller package area and non-significant increase of package cost with the increase in the number of packaged chips, compared with the relatively conventional wire bonding method. In the TSV bonding method, fine vias are formed through each semiconductor silicon chip, namely extending from the frontside to the backside of the semiconductor silicon chip, and then the stacked silicon chips are electrically connected to one another. As semiconductor silicon chips are bonded in a three dimensional and vertical way, bonding leads arranged between the silicon chips can be greatly shortened and a final device can be significantly improved in terms of volume, performance and signal access and transmission speed.
As the TSV bonding method requires exposure to the backside of a wafer, relevant semiconductor lithography devices are required to be equipped with a backside alignment apparatus which uses a pattern formed on a frontside (or a top surface) of the wafer as a reference mark for a backside (or a bottom surface) of the wafer to determine a deviation between positions of the pattern formed on the frontside and a pattern to be exposed on the backside of the wafer. Thus, measuring precision of the backside alignment apparatus critically determines the overlay errors between patterns formed on the frontside and backside.
Currently, there are mainly two methods for carrying out backside alignment of a wafer, namely visual light measuring method and infrared light measuring method. In a visual light measuring method, a light-path turning device and an imaging device are arranged on opposite sides under a wafer stage for illuminating and imaging a backside reference mark of the wafer using a visual light. While in an infrared light measuring method, a backside reference mark of the wafer is illuminated and imaged by using the wafer penetrating property of the infrared light. However, the above two methods for carrying out backside alignment for a wafer each have advantages and disadvantages in configuration.
U.S. Pat. Nos. 6,525,805B and 6,768,539B respectively disclose a typical backside alignment apparatus, which uses an off-axis alignment apparatus to achieve wafer backside alignment with visual light measuring method. However, as too many illumination devices for illuminating backside alignment marks are incorporated in this apparatus, each backside alignment mark corresponding to a set of illumination devices, it is complicated and expensive to assemble these illumination devices together. Moreover, its design of arranging the illumination devices under a wafer stage leads to a high complexity and processing cost in structure design of the wafer stage. Furthermore, as each of the backside alignment marks must be positioned within an illumination field of its associated illumination devices, the apparatus has poor process adaptation.
Moreover, U.S. Pat. No. 6,525,805B also discloses a backside alignment apparatus using infrared light measuring method. In this apparatus, near-infrared light sources are arranged at different positions within the wafer stage for illuminating backside alignment marks of the wafer, and a near-infrared imaging device is disposed above the wafer for imaging the alignment marks. As illumination devices for illuminating backside marks of the wafer are arranged within the wafer stage, the structure design and assembly of the wafer stage are complicated and may have a high processing cost; moreover, the structure design may be restricted by the overall alignment accuracy of the wafer and space size of the wafer stage. Furthermore, alignment marks need to be formed at predetermined positions to co-work with the backside mark illumination devices, thus increasing process steps and complexity and leading to a poor process adaptation.